• Corpus ID: 244102746

Elastic Silicon Interconnects: Abstracting Communication in Accelerator Design

@article{Demme2021ElasticSI,
  title={Elastic Silicon Interconnects: Abstracting Communication in Accelerator Design},
  author={John Demme},
  journal={ArXiv},
  year={2021},
  volume={abs/2111.06584}
}
  • J. Demme
  • Published 12 November 2021
  • Engineering
  • ArXiv
ing Communication in Accelerator Design John Demme john.demme@microsoft.com Microsoft, USA 

Figures from this paper

References

SHOWING 1-7 OF 7 REFERENCES

PNoC: a flexible circuit-switched NoC for FPGA-based systems

A new lightweight circuit-switched architecture called programmable NoC (PNoC) is described, a flexible architecture suitable for use in FPGA-based systems that resulted in as much as a 23/spl times/ speedup compared with a shared bus implementation.

The Case for Embedded Networks on Chip on Field-Programmable Gate Arrays

The authors propose augmenting the FPGA architecture with an embedded NoC to implement the system-level communication infrastructure and mitigate the hardware design challenges faced by current bus-based interconnects.

Theory of latency-insensitive design

The theory of latency-insensitive design is presented as the foundation of a new correct-by-construction methodology to design complex systems by assembling intellectual property components to design large digital integrated circuits by using deep submicrometer technologies.

Software-Driven Hardware Development

The Connectal framework is presented, which enables the development of hardware accelerators for software applications by generating hardware/software interface implementations from abstract Interface Design Language (IDL) specifications.

The LEAP FPGA operating system

This work presents the Latency-insensitive Environment for Application Programming (LEAP), an FPGA operating system built around latency-insensitivity communications channels, and presents an extensible interface for compile-time management of resources.

Elastic Circuits

Synchronous and asynchronous elastic circuits can be designed, analyzed, and optimized using similar techniques, and choices between synchronous and asynchronous implementations are localized and deferred until late in the design process.

CONNECT: re-examining conventional wisdom for designing nocs in the context of FPGAs

This paper developed CONNECT, an NoC generator that can produce synthesizable RTL designs of FPGA-tuned multi-node NoCs of arbitrary topology that uniquely influence key NoC design decisions, such as topology, link width, router pipeline depth, network buffer sizing, and flow control.