Efficient wireless Digital Up Converters design using system generator

@article{Wei2008EfficientWD,
  title={Efficient wireless Digital Up Converters design using system generator},
  author={Wang Wei and Zeng Yifang and Yan Yang},
  journal={2008 9th International Conference on Signal Processing},
  year={2008},
  pages={443-446}
}
A WCDMA Digital Up Converter (DUC) design based on FPGA is presented. Aiming to shorten the design period and increase the design performance, a powerful design tool, Xilinx System Generator is used. The RRC filter and the Half-band filter are designed by using MATLAB FDATool, and implemented by using Xilinx FIR Compiler. The DDS module is generated by Xilinx DDS Compiler. Finally, the DUC design is implemented into Xilinx XC5VSX50T device. Using Vitex-5 DSP48E slices, the complex-multiplier… CONTINUE READING

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