Efficient verification of determinate speed-independent circuits

  title={Efficient verification of determinate speed-independent circuits},
  author={Peter A. Beerel and Jerry R. Burch and Teresa H. Y. Meng},
We present sufficient conditions for the correctness of speedindependent circuits with respect to their state graph (SC) specification, which can be tested in linear-time with respect to the size of the SG. Our correctness conditions consist of one safety condition and one progress condition. The progress condition detects deadloek conditions that are not present in the specification. The SG specifications eonsidered me determinate, allowing input choice (eonditiomds) but not output choice… CONTINUE READING
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