Efficient technique to reduce power dissipation of Op-Amps at high speed

  title={Efficient technique to reduce power dissipation of Op-Amps at high speed},
  author={Avaneesh K. Dubey and Pankaj Srivastava and Manisha Pattanaik},
  journal={2015 International Conference on Robotics, Automation, Control and Embedded Systems (RACE)},
To draw an accurate relationship between power dissipation and speed is a challenging problem in operational Amplifier with switch capacitance. However, transformation of current steer circuit into charge steer is an efficient technique to reduce power dissipation even at higher speed. In this paper, an efficient model is proposed to estimate the 1st and 2nd stage operational Amplifier's power dissipation and delay, which can further used to design higher order Operational Amplifier, Voltage… CONTINUE READING

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Publications referenced by this paper.
Showing 1-6 of 6 references

Charge steering: A low-power design paradigm

Proceedings of the IEEE 2013 Custom Integrated Circuits Conference • 2013
View 3 Excerpts
Highly Influenced

Step response analysis of third order OpAmps With slew-rate

2013 IFIP/IEEE 21st International Conference on Very Large Scale Integration (VLSI-SoC) • 2013
View 1 Excerpt

Clock gating for power optimization in ASIC design cycle theory & practice

Proceeding of the 13th international symposium on Low power electronics and design (ISLPED '08) • 2008
View 1 Excerpt