Efficient partitioning and analysis of digital CMOS-circuits

  title={Efficient partitioning and analysis of digital CMOS-circuits},
  author={Uwe H{\"u}bner and Heinrich Theodor Vierhaus},
Considerable work has been done in the area of performance optimization for ATPG algorithms. Whereas the application of high-performance algorithms is often limited to trivial gates as ANDs, ORs, and XORs, the cell libraries of silicon vendors contain more sophisticated structures. As a step towards the automatic test generation for even irregular transistor si?uctures, a library independent algorithm is presented for the partitioning and analysis of switch level CMOS circuits. 
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