Efficient layout generation and evaluation of vertical channel devices

@article{Wang2014EfficientLG,
  title={Efficient layout generation and evaluation of vertical channel devices},
  author={Wei-Che Wang and Puneet Gupta},
  journal={2014 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)},
  year={2014},
  pages={550-556}
}
  • Wei-Che Wang, Puneet Gupta
  • Published in
    IEEE/ACM International…
    2014
  • Computer Science
  • Vertical gate-all-around (VGAA) has been shown to be one of the most promising devices for the scaling beyond 10nm for its reduced delay, large driving current, and good gate control. Moreover, emerging devices such as heterojunction tunneling FETs are more amenable to vertical fabrication. However, past studies of vertical channel devices focused more on regular memory architectures and simple standard cells like inverter. Since naive migration of regular FinFET layouts to vertical FETs yields… CONTINUE READING

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