Efficient instruction schedulers for SMT processors


We propose dynamic scheduler designs to improve the scheduler scalability and reduce its complexity in the SMT processors. Our first design is an adaptation of the recently proposed instruction packing to SMT. Instruction packing opportunistically packs two instructions (possibly from different threads), each with at most one non-ready source operand at the… (More)
DOI: 10.1109/HPCA.2006.1598137


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@article{Sharkey2006EfficientIS, title={Efficient instruction schedulers for SMT processors}, author={Joseph J. Sharkey and Dmitry V. Ponomarev}, journal={The Twelfth International Symposium on High-Performance Computer Architecture, 2006.}, year={2006}, pages={288-298} }