Efficient hardware architecture for direct 2D DCT computation and its FPGA implementation

@article{Hatim2013EfficientHA,
  title={Efficient hardware architecture for direct 2D DCT computation and its FPGA implementation},
  author={A. Hatim and S. Belkouch and T. Sadiki and M. Hassani},
  journal={2013 25th International Conference on Microelectronics (ICM)},
  year={2013},
  pages={1-4}
}
In this paper, we propose a low complexity architecture for direct 2D-DCT computation. The architecture will transform the pixels from spatial to spectral domain with the required quality constraints of the compression standards. In our previous works we introduced a new fast 2D_DCT with low computations: only 40 additions are used and no multiplications are needed. Based on that algorithm we developed in this work a new architecture to achieve the computations of the 2D DCT directly without… Expand
3 Citations

References

SHOWING 1-10 OF 19 REFERENCES
Low complexity DCT engine for image and video compression
  • 9
  • PDF
A Pipelined Fast 2D-DCT Accelerator for FPGA-based SoCs
  • 51
  • PDF
Design optimization of the quantization and a pipelined 2D-DCT for real-time applications
  • 7
Optimized Architecture Using a Novel Subexpression Elimination on Loeffler Algorithm for DCT-Based Image Compression
  • 10
  • PDF
FPGA implementation of pipelined 2D-DCT and quantization architecture for JPEG image compression
  • 39
Transposed-Memory Free Implementation for Cost-Effective 2D-DCT Processor
  • 6
An improved scaled DCT architecture
  • 33
Low-power VLSI architectures for 3D discrete cosine transform (DCT)
  • 14
An efficient joint implementation of three stages for fast computation of color space conversation in image coding/decoding
  • 7
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