Efficient diminished-1 modulo 2/sup n/ + 1 multipliers

@article{Efstathiou2005EfficientDM,
  title={Efficient diminished-1 modulo 2/sup n/ + 1 multipliers},
  author={Costas Efstathiou and Haridimos T. Vergos and Giorgos Dimitrakopoulos and Dimitris Nikolos},
  journal={IEEE Transactions on Computers},
  year={2005},
  volume={54},
  pages={491-496}
}
In this work, we propose a new algorithm for designing diminished-1 modulo 2/sup n/+1multipliers. The implementation of the proposed algorithm requires n + 3 partial products that are reduced by a tree architecture into two summands, which are finally added by a diminished-1 modulo 2/sup n/+1 adder. The proposed multipliers, compared to existing implementations, offer enhanced operation speed and their regular structure allows efficient VLSI implementations. 
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References

Publications referenced by this paper.
Showing 1-10 of 24 references

A Simplified Architecture for Modulo ð2 þ 1Þ Multiplication

Y. Ma
IEEE Trans. Computers, vol. 47, no. 3, pp. 333-337, Mar. 1998. • 1998
View 10 Excerpts
Highly Influenced

A 177 Mb/s VLSI Implementation of the International Data Encryption Algorithm

R. Zimmermann
IEEE J. Solid-State Circuits, vol. 29, no. 3, pp. 303-307, 1994. • 1994
View 5 Excerpts
Highly Influenced

Efficient VLSI Implementation of Modulo (2^n=B11) Addition and Multiplication

IEEE Symposium on Computer Arithmetic • 1999
View 4 Excerpts
Highly Influenced

A New Modulo 2a + 1 Multiplier

View 4 Excerpts
Highly Influenced

A Memoryless modð2 1Þ Residue Multiplier

A. A. Hiasat
Electronics Letters, vol. 28, no. 3, pp. 314-315, 1992. • 1992
View 5 Excerpts
Highly Influenced

Regular VLSI Architectures for Multiplication Modulo (2 þ 1)

A. V. Curiger
IEEE J. Solid-State Circuits, vol. 26, no. 7, pp. 990-994, 1991. • 1991
View 5 Excerpts
Highly Influenced

Modulo 2 1 Adder Design Using Select-Prefix Blocks

C. Efstathiou
IEEE Trans. Computers, vol. 52, pp. 1399-1406, 2003. • 2003
View 2 Excerpts

RDSP: a RISC DSP based on residue number system

Euromicro Symposium on Digital System Design, 2003. Proceedings. • 2003
View 1 Excerpt

Diminished-One Modulo 2 þ 1 Adder Design

H. T. Vergos, C. Efstathiou, D. Nikolos
IEEE Trans. Computers, vol. 51, pp. 1389-1399, 2002. • 2002

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