Efficient digital baseline wander algorithm and its architecture for fast Ethernet

  title={Efficient digital baseline wander algorithm and its architecture for fast Ethernet},
  author={J. H. Baek and J. H. Hong and M. H. Sunwoo and K. U. Kim},
  journal={IEEE Workshop onSignal Processing Systems, 2004. SIPS 2004.},
The paper proposes an efficient digital baseline wander (BLW) algorithm and its hardware architecture for 100BASE-TX Ethernet. The proposed BLW compensator uses four symbols, including the present symbol, and can remove BLW at the channel having large BLW or having a killing packet. The proposed BLW compensator is purely implemented in a digital domain. To verify the performance of the proposed BLW compensator, we simulate a 100BASE-TX DSP submodule using the SPW/spl trade/ tool. The DSP… CONTINUE READING
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