Efficient capacitance extraction method for interconnects with dummy fills

@article{Kurokawa2004EfficientCE,
  title={Efficient capacitance extraction method for interconnects with dummy fills},
  author={Atsushi Kurokawa and Toshiki Kanamoto and Akira Kasebe and Yasuaki Inoue and Hiroo Masuda},
  journal={Proceedings of the IEEE 2004 Custom Integrated Circuits Conference (IEEE Cat. No.04CH37571)},
  year={2004},
  pages={485-488}
}
The accuracy of parasitic extraction has become increasingly important for system-on-chip (SoC) designs. In this paper, we present a practical method of dealing with the influences of floating dummy metal fills, which are inserted to assist planarization by the chemical-mechanical polishing (CMP) process, in extracting interconnect capacitances. The method is based on reducing the thicknesses of dummy metal layers according to electrical field theory. We also clarify the influences of dummy… CONTINUE READING
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