• Corpus ID: 7542775

Efficient and compatible VLSI architecture of parallel MAC based on high radix modified Booth algorithm

@inproceedings{Tapashetti2016EfficientAC,
  title={Efficient and compatible VLSI architecture of parallel MAC based on high radix modified Booth algorithm},
  author={Pratibhadevi Tapashetti and D. B. Kulkarni},
  year={2016}
}
In the current scenarios there is a requirement for high speed applications of digital signal processing. This need high speed low power, less delay and compact circuits. Multiplication and addition are the major required operations for digital signal processing. This need is fulfilled by using new architectures for modified booth algorithm, carry save adder and Wallace tree. Modified booth algorithm increases the speed by reducing the number of partial products and carry save adder performs… 
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Tables from this paper

Implementation of High Speed MAC VLSI Architectures, Based on High Radix Modified Booth Algorithm

TLDR
The proposed architecture uses modified booth algorithm, Wallace tree and carry save adder to reduce the partial products and CSA is utilized for improving the design speed.

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