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@inproceedings{Zhang2002EfficientVA, title={Efficient VLSI Architectures for Error-Correcting Coding}, author={Tong Zhang and Keshab K. Parhi and Georgios G. Giannakis}, year={2002} }

- Published 2002

This thesis is devoted to several efficient VLSI architecture design issues in errorcorrecting coding, including finite field arithmetic, (Generalized) Low-Density ParityCheck (LDPC) codes, and Reed-Solomon codes. A systematic low-complexity bit-parallel finite field multiplier design approach is proposed. This design approach is applicable to GF (2m) constructed by arbitrary irreducible polynomials. It effectively exploits the spatial correlation in the bit-parallel finite field multiplication… CONTINUE READING

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