Corpus ID: 33712887

Efficient VLSI Architectures for Error-Correcting Coding

@inproceedings{Zhang2002EfficientVA,
  title={Efficient VLSI Architectures for Error-Correcting Coding},
  author={T. Zhang and K. Parhi and G. Giannakis},
  year={2002}
}
  • T. Zhang, K. Parhi, G. Giannakis
  • Published 2002
  • Computer Science
  • This thesis is devoted to several efficient VLSI architecture design issues in errorcorrecting coding, including finite field arithmetic, (Generalized) Low-Density ParityCheck (LDPC) codes, and Reed-Solomon codes. A systematic low-complexity bit-parallel finite field multiplier design approach is proposed. This design approach is applicable to GF (2m) constructed by arbitrary irreducible polynomials. It effectively exploits the spatial correlation in the bit-parallel finite field multiplication… CONTINUE READING
    Configurable LDPC Decoder Architectures for Regular and Irregular Codes
    18
    Memory System Optimization for FPGA-Based Implementation of Quasi-Cyclic LDPC Codes Decoders
    63
    Semi-parallel reconfigurable architectures for real-time LDPC decoding
    128
    A REDUCED-COMPLEXITY LDPC DECODING ALGORITHM WITH CHEBYSHEV POLYNOMIAL FITTING
    Flexible low-complexity decoding architecture for QC-LDPC codes
    Symbol-flipping based decoding of generalized low-density parity-check codes over GF(q)
    11
    Design and Realization of Analog Phi-Function for LDPC Decoder
    Design of Encoder and Decoder for LDPC Codes Using Hybrid H-Matrix
    13

    References

    Publications referenced by this paper.
    SHOWING 1-10 OF 85 REFERENCES
    VLSI Designs for Multiplication over Finite Fields GF (2m)
    142
    Efficient encoding of low-density parity-check codes
    987
    High-speed architectures for Reed-Solomon decoders
    276
    Bit-serial Reed - Solomon encoders
    258
    Systematic design approach of Mastrovito multipliers over GF(2/sup m/)
    7