Efficient Use of Memory Bandwidth to Improve Network Processor Throughput

@inproceedings{Hasan2003EfficientUO,
  title={Efficient Use of Memory Bandwidth to Improve Network Processor Throughput},
  author={Jahangir Hasan and Satish Chandra and T. N. Vijaykumar},
  booktitle={ISCA},
  year={2003}
}
We consider the efficiency of packet buffers used in packet switches built using network processors (NPs). Packet buffers are typically implemented using DRAM, which provides plentiful buffering at a reasonable cost. The problem we address is that a typical NP workload may be unable to utilize the peak DRAM bandwidth. Since the bandwidth of the packet buffer is often the bottleneck in the performance of a shared-memory packet switch, inefficient use of available DRAM bandwidth further reduces… CONTINUE READING
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