Efficient Timing Channel Protection for On-Chip Networks

@article{Wang2012EfficientTC,
  title={Efficient Timing Channel Protection for On-Chip Networks},
  author={Yao Wang and G. Edward Suh},
  journal={2012 IEEE/ACM Sixth International Symposium on Networks-on-Chip},
  year={2012},
  pages={142-151}
}
On-chip network is often dynamically shared among applications that are concurrently running on a chip-multiprocessor (CMP). In general, such shared resources imply that applications can affect each other's timing characteristics through interference in shared resources. For example, in on-chip networks, multiple flows can compete for links and buffers. We show that this interference is an attack vector through which a malicious application may be able to infer data-dependent information about… CONTINUE READING
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References

Publications referenced by this paper.
Showing 1-10 of 14 references

Composable Resource Sharing Based on Latency-Rate Servers

2009 12th Euromicro Conference on Digital System Design, Architectures, Methods and Tools • 2009
View 1 Excerpt

Preemptive Virtual Clock: A flexible, efficient, and cost-effective QOS scheme for networks-on-chip

2009 42nd Annual IEEE/ACM International Symposium on Microarchitecture (MICRO) • 2009
View 2 Excerpts

Covert and Side Channels Due to Processor Architecture

2006 22nd Annual Computer Security Applications Conference (ACSAC'06) • 2006

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