Efficient Timed Reachability Analysis using Clock Difference Diagrams

@inproceedings{Behrmann1998EfficientTR,
  title={Efficient Timed Reachability Analysis using Clock Difference Diagrams},
  author={Gerd Behrmann and Kim G. Larsen and Justin Pearson and Carsten Weise and Wang Yi},
  year={1998}
}
One of the major problems in applying automatic verication tools to industrial-size systems is the excessive amount of memory required during the state-space exploration of a model. In the setting of real-time, this problem of state-explosion requires extra attention as information must be kept not only on the discrete control structure but also on the values of continuous clock variables. In this paper, we present Clock Dierence Diagrams, CDD's, a BDD-like data-structure for representing and… CONTINUE READING

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Key Quantitative Results

  • Our experimental results demonstrate signicant space-savings: for 8 industrial examples, the savings are between 46% and 99% with moderate increase in runtime.

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