Efficient STT-RAM last-level-cache architecture to replace DRAM cache

@inproceedings{Hameed2017EfficientSL,
  title={Efficient STT-RAM last-level-cache architecture to replace DRAM cache},
  author={Fazal Hameed and Christian Menard and Jer{\'o}nimo Castrill{\'o}n},
  booktitle={MEMSYS},
  year={2017}
}
Recent research has proposed die-stacked Last Level Cache (LLC) to overcome the Memory Wall. Lately, Spin-Transfer-Torque Random Access Memory (STT-RAM) caches have been recommended as they provide improved energy efficiency compared to DRAM caches. However, the recently proposed STT-RAM cache architecture unnecessarily dissipates energy by fetching… CONTINUE READING