Efficient Realization of Data Dependencies in Algorithm Partitioning Under Resource Constraints

@inproceedings{Siegel2006EfficientRO,
  title={Efficient Realization of Data Dependencies in Algorithm Partitioning Under Resource Constraints},
  author={S. Siegel and R. Merker},
  booktitle={Euro-Par},
  year={2006}
}
  • S. Siegel, R. Merker
  • Published in Euro-Par 2006
  • Computer Science
  • Mapping algorithms to parallel architectures efficiently is very important for a cost-effective design of many modern technical products. In this paper, we present a solution to the problem of efficiently realizing uniform data dependencies on processor arrays. In contrary to existing approaches, we formulate an optimization problem to consider the cost of both: channels and registers. Further, a solution to the optimization problem assigns which channels shall be implemented and it specifies… CONTINUE READING
    5 Citations
    Minimum Cost for Channels and Registers in Processor Arrays by Avoiding Redundancy
    • S. Siegel, R. Merker
    • Computer Science
    • IEEE 17th International Conference on Application-specific Systems, Architectures and Processors (ASAP'06)
    • 2006
    • 7
    • PDF
    A design methodology for automatic generation of processor arrays based on the polytope model
    A parallelization methodology for reconfigurable systems applied to edge detection
    • 1
    • Highly Influenced

    References

    SHOWING 1-10 OF 17 REFERENCES
    Algorithm Partitioning including Optimized Data-Reuse for Processor Arrays
    • 4
    Minimum Cost for Channels and Registers in Processor Arrays by Avoiding Redundancy
    • S. Siegel, R. Merker
    • Computer Science
    • IEEE 17th International Conference on Application-specific Systems, Architectures and Processors (ASAP'06)
    • 2006
    • 7
    • PDF
    Resource-constrained scheduling of partitioned algorithms on processor arrays
    • 22
    • PDF
    Resource constrained scheduling of uniform algorithms
    • L. Thiele
    • Computer Science
    • J. VLSI Signal Process.
    • 1995
    • 55
    Optimal loop scheduling with register constraints using flow graphs
    • Jan Müller, D. Fimmel, R. Merker
    • Computer Science
    • 7th International Symposium on Parallel Architectures, Algorithms and Networks, 2004. Proceedings.
    • 2004
    • 10
    Optimized data-reuse in processor arrays
    • 3
    Localization of Data Transfer in Processor Arrays
    • 5
    Optimal Loop Parallelization under Register Constraints
    • 22
    Fine-Grain Scheduling under Resource Constraints
    • 50
    Combined instruction and loop parallelism in array synthesis for FPGAs
    • 21
    • PDF