Efficient Procedure Mapping Using Cache Line Coloring

  title={Efficient Procedure Mapping Using Cache Line Coloring},
  author={Amir H. Hashemi and David R. Kaeli and Brad Calder},
As the gap between memory and processor performance continues to widen, it becomes increasingly important to exploit cache memory eflectively. Both hardware and aoftware approaches can be explored to optimize cache performance. Hardware designers focus on cache organization issues, including replacement policy, associativity, line size and the resulting cache access time. Software writers use various optimization techniques, including software prefetching, data scheduling and code reordering… CONTINUE READING
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