Efficient MLP digital implementation on FPGA


The efficiency and the accuracy of a digital feedforward neural networks must be optimized to obtain both high classification rate and minimum area on chip. In this paper an efficient MLP digital implementation. The key features of the hardware implementation are the virtual neuron based architecture and the use of the sinusoidal activation function for the… (More)
DOI: 10.1109/DSD.2005.38


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Citations per Year

Citation Velocity: 7

Averaging 7 citations per year over the last 3 years.

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