Efficient Instruction Cache Simulation and Execution Profiling with a Threaded-Code Interpreter

Abstract

We present an extension to an existing SPARC V8 instruction set simulator, SimICS, to support accurate profiling of branches and instruction cache misses. SimICS had previously supported profiling data cache efficiency and virtual memory performance (TLB misses), and estimated execution profiling using sampling. The new design allows a system-level… (More)
DOI: 10.1145/268437.268745

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