Efficient High Speed Compression Trees on Xilinx FPGAs

@inproceedings{Kumm2014EfficientHS,
  title={Efficient High Speed Compression Trees on Xilinx FPGAs},
  author={Martin Kumm and Peter Zipf},
  booktitle={MBMV},
  year={2014}
}
Compressor trees are efficient circuits to realize multi-operand addition with fast carry-save arithmetic. They can be found in various arithmetic applications like multiplication, squaring and the evaluation of polynomials with application to function approximation. Finding good elementary compressing elements on FPGAs is a non-trivial task as an efficient mapping to look-up tables and carry-chain logic has to be found. It was shown recently that common ternary adders on modern FPGAs… CONTINUE READING
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and Bogdan Popa: Arithmetic Core Generation Using Bit Heaps

  • Brunie, Nicolas, Florent de Dinechin, Matei Istoan, Guillaume Sergent, Kinga Illyes
  • Field Programmable Logic and Applications (FPL…
  • 2013
Highly Influential
14 Excerpts

and P

  • H. Parandeh-Afshar, A. Neogy, P. Brisk
  • Ienne: Compressor Tree Synthesis on Commercial…
  • 2011
Highly Influential
11 Excerpts

Martin and Peter Zipf: High Speed Low Complexity FPGA-Based FIR Filters Using Pipelined Adder Graphs

  • Kumm
  • IEEE International Conference on…
  • 2011
Highly Influential
1 Excerpt

J

  • Hormigo
  • J Villalba, and E L Zapata: Multioperand…
  • 2013
1 Excerpt

and Uwe MeyerBaese: Multiple Constant Multiplication with Ternary Adders

  • Kumm, Martin, Martin Hardieck, Jens Willkomm, Peter Zipf
  • IEEE International Conference on Field…
  • 2013
8 Excerpts

Florent de and Bogdan Pasca: Designing Custom Arithmetic Data Paths with FloPoCo

  • Dinechin
  • IEEE Design & Test of Computers, 28(4):18–27,
  • 2012

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