Efficient Generation of Test Patterns Using Boolean Difference

  title={Efficient Generation of Test Patterns Using Boolean Difference},
  author={Tracy Larrabee},
A combinational circuit can be tested for the presence of a single stuck-at fault by applying a set of inputs that excite a verifiable output response in that circuit. If the fault is present, the output will be different than it would be if the fault were not present. Given a circuit, the goal of an automatic test pattern generation system is to generate a set of input sets that will detect every possible single stuck-at fault in the circuit. These two papers describe a new method for… CONTINUE READING
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Fault Simulation for Structured VLSI

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2 Excerpts

The Complexity of Theorem Proving Procedures

  • T. Shirnono

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