Efficient Finite Field Processor for GF(2^163) and its VLSI Implementation

@article{Ansari2007EfficientFF,
  title={Efficient Finite Field Processor for GF(2^163) and its VLSI Implementation},
  author={B. Ansari and H. Wu},
  journal={Fourth International Conference on Information Technology (ITNG'07)},
  year={2007},
  pages={1021-1026}
}
  • B. Ansari, H. Wu
  • Published 2007
  • Computer Science
  • Fourth International Conference on Information Technology (ITNG'07)
A high performance finite field processor for elliptic curve cryptography is presented. One of the contributions in this work is the modified bit-parallel word-serial (BPWS) finite field multiplication algorithm and its corresponding pipeline-fashion multiplier architecture. The proposed multiplier achieves a throughput of one multiplication every N + 1 clock cycles, in contrast with at least N + 3 clock cycles required in the recent other designs, where N is the ratio of field size to word… Expand
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