Efficient Field Processing Cores in an Innovative Protocol Processor System-on-Chip

  title={Efficient Field Processing Cores in an Innovative Protocol Processor System-on-Chip},
  author={George Lykakis and N. Mouratidis and Kyriakos Vlachos and Nikos A. Nikolaou and Stylianos Perissakis and G. Sourdis and George E. Konstantoulakis and Dionisios N. Pnevmatikatos and Dionysios I. Reisis},
We present an innovative protocol processor component that combines wire-speed processing for low-level, and best effort processing for higher-level protocols. The component is a System-on-Chip that integrates variable size packet buffering, specialised cores for header and field processing, generic RISC cores and scheduling blocks. We focus on the main innovation, the reprogrammable pipeline module, and discuss its internal architecture, optimised to perform field processing on byte streams… CONTINUE READING


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