Efficient DSP architecture for Viterbi decoding with small trace back latency

@article{Park2004EfficientDA,
  title={Efficient DSP architecture for Viterbi decoding with small trace back latency},
  author={Weon Heum Park and Myung Hoon Sunwoo and Seong Keun Oh},
  journal={The 2004 IEEE Asia-Pacific Conference on Circuits and Systems, 2004. Proceedings.},
  year={2004},
  volume={1},
  pages={129-132 vol.1}
}
This work proposes specialized DSP instructions and their hardware architecture for the Viterbi algorithm. The proposed architecture can reduce the trace back (TB) latency and can support various wireless communication standards. The proposed instructions perform the add compare select (ACS) and TB operations in parallel and the architecture has special hardware, called the offset calculation unit (OCU), which automatically calculates data addresses for acceleration of the trellis butterfly… CONTINUE READING