Efficient Congestion-Oriented Custom Network-on-Chip Topology Synthesis

  title={Efficient Congestion-Oriented Custom Network-on-Chip Topology Synthesis},
  author={Cristinel Ababei},
  journal={2010 International Conference on Reconfigurable Computing and FPGAs},
We propose a new custom Network-on-Chip (NoC) topology synthesis methodology consisting of floor planning, routers assignment, and routing paths calculation steps. The proposed heuristic methodology integrates fast algorithms based on the B*-tree representation for floor planning, on bipartite matching for the routers assignment step, and on multi commodity flow for congestion minimization for the routing paths calculation step. Hence, it is able to explore a large portion of the solution space… CONTINUE READING
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