An interactive CAD methodology is presented for designing digital filters with optimised discrete coefficients. The objective is to minimise the cost of integration C() subject to the constraint that the desired specifications on the complex frequency transfer function H(w,a) are satisfied, The vector represents the fixed coefficients in the filter network. For VLSI DSP architectures, where multiplication is implemented using software controlled or hardwired shift—and—add operations, 0(a) is defined as the total number of non—zero bits in the discrete representation of a. An accurate multiparameter analysis technique, based on the bilinear property of H(w,a), is exploited to develop numerically reliable and cornputationally efficient tools for function evaluation and feasible region determination. These are built into a CAD framework together with tools for computing C(s) and predicting the location of the minima of C(a) Extremely fast optimisation strategies using this framework are demonstrated, for different filter topologies with up to 10 coefficients.