Efficient Addition on Field Programmable Gate Arrays

  title={Efficient Addition on Field Programmable Gate Arrays},
  author={Andreas Jakoby and Christian Schindelhauer},
We investigate average efficient adders for grid-based environments related to current Field Programmable Gate Arrays (FPGAs) and VLSI-circuits. Motivated by current trends in FPGA hardware design we introduce a new computational model, called the λ -wired grid model. The parameter λ describes the degree of connectivity of the underlying hardware. This model covers among others two-dimensional cellular automata for λ = 0 and VLSI-circuits for λ = 1. To formalize input and output constraints of… 
1 Citations
Improving the average delay of sorting


Programmable active memories: reconfigurable systems come of age
This work exhibits a dozen applications where PAM technology proves superior, both in performance and cost, to every other existing technology, including supercomputers, massively parallel machines, and conventional custom hardware.
Reconfigurable Computing for Digital Signal Processing: A Survey
It is shown that while contemporary reconfigurable computing can be applied to a variety of DSP applications including video, audio, speech, and control, much work remains to realize its full potential.
The Average Time Complexity to Compute Prefix Functions in Processor Networks
  • A. Jakoby
  • Computer Science, Mathematics
  • 1999
The average case complexity of a computational problem for arbitrary strictly positive input distributions is defined and a network design is presented that achieves the optimal delay for all prefix functions and all inputs of a given length while keeping the network size linear.
An efficient implementation of Boolean functions nd finite state machine as self-timed circuit
The synthesized CLs and FSMs can serve as "correct-by-construction" building blocks for self-timed silicon system compilation and are shown to require less gates than other proposed methods.
Circuit complexity: from the worst case to the average case
Inspired by recent successful attempts to develop a meaningful average case analysis for TM computations, a new comlexity measure for the internal delay is defined, called time, which is defined by considering the complexity of circuits with uniform distributed random input bits that generate such distributions.
Probabilistic parallel prefix computation
  • J. Reif
  • Computer Science, Mathematics
  • 1993
Reconfigurable computing: a survey of systems and software
The hardware aspects of reconfigurable computing machines, from single chip architectures to multi-chip systems, including internal structures and external coupling are explored, and the software that targets these machines is focused on.
An architecture for electrically configurable gate arrays
A novel architecture for CMOS electrically configurable gate arrays using a two-terminal antifuse element is described, which can provide a level of integration comparable to mask-programmable gate arrays.
Average case complexity of unbounded fanin circuits
  • A. Jakoby, R. Reischuk
  • Computer Science
    Proceedings 15th Annual IEEE Conference on Computational Complexity
  • 2000
It is shown that only two cases can occur: a parallel prefix functions f either has the same average complexity as PARITY, that is the average delay has to be of order O(log n/ loglog s) for circuits of size s, or f can be computed with constant average delay and almost linear size there is no complexity level in between.
On Parallel Prefix Computation
We prove that prefix sums of n integers of at most b bits can be found on a COMMON CRCW PRAM in time with a linear time-processor product. The algorithm is optimally fast, for any polynomial number