Effects of Memory Latencies on Non-Blocking Processor/Cache Architectures

@inproceedings{ner1993EffectsOM,
  title={Effects of Memory Latencies on Non-Blocking Processor/Cache Architectures},
  author={Koray {\"O}ner and Michel Dubois},
  booktitle={International Conference on Supercomputing},
  year={1993}
}
In this paper, we introduce a simple hardware mechanism supporting non-blocking loads in conjunction with lockup-free caches to hide memory latencies in high-performance processors. The cache and processor cooperate on load misses so that the overall complexity of the non-blocking mechanisms in the cache and in the processor is greatly reduced. We use detailed simulations to evaluate the effectiveness of the architecture and of a simple compiler transformation at hiding miss latencies of up to… CONTINUE READING
6 Citations
4 References
Similar Papers

References

Publications referenced by this paper.
Showing 1-4 of 4 references

Non-blocking caches for high performance

  • M. Franklin, G. Sohi
  • 1991
Highly Influential
4 Excerpts

LLNL Fortran Kernels: MFk)ps

  • F. H. McMahon
  • Technical Repom Lawrence Livermore Laboratories,
  • 1984
Highly Influential
2 Excerpts

Similar Papers

Loading similar papers…