Corpus ID: 41792896

Effects of Different Clock Gating Techinques on Design

@inproceedings{Sharma2012EffectsOD,
  title={Effects of Different Clock Gating Techinques on Design},
  author={Dushyant Kumar Sharma},
  year={2012}
}
Low power is one of the most important issues in today's ASIC (Application Specific Intregated Circuit) design. As the transistor is scaled down, power density becomes high and there is urgent need of reduction in power. The clock gating is one of the most elegant and classic techniques for reduction of power. Clock gating can be implemented by using any of these three cells, (1) Latch based cell (2) Flip-Flop based cell (3) Gate based cell. In this paper, we demonstrate the effect of different… Expand

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