Effective implementation of floating-point adder using pipelined LOP in FPGAs

@article{Malik2005EffectiveIO,
  title={Effective implementation of floating-point adder using pipelined LOP in FPGAs},
  author={Ali Malik and Seok-Bum Ko},
  journal={Canadian Conference on Electrical and Computer Engineering, 2005.},
  year={2005},
  pages={706-709}
}
The current intellectual property provided by Xilinx for floating-point adder is not competitive and versatile. This paper presents a hardware implementation of IEEE 754 compliant floating-point adder and a design methodology for floating-point adder with leading-one predictor (LOP). LOP has been used to predict the shift amount for post normalization in parallel with the addition. In some cases, however, there is an error in prediction. LOP used in our design detects this error concurrently… CONTINUE READING

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