Effective hardware-level thread synchronization for high performance and power efficiency in application specific multi-threaded embedded processors

Abstract

Multi-threaded processors interleave the execution of several threads to reduce processor stalling time. Instruction cache misses usually account for a significant fraction of the overall stalling time due to frequent instruction fetches. Apart from incurring extended execution time (hence its direct impact on energy consumption), cache misses also lead to… (More)
DOI: 10.1109/ICCD.2015.7357119

Topics

9 Figures and Tables

Cite this paper

@article{Wickramasinghe2015EffectiveHT, title={Effective hardware-level thread synchronization for high performance and power efficiency in application specific multi-threaded embedded processors}, author={Mahanama Wickramasinghe and Hui Guo}, journal={2015 33rd IEEE International Conference on Computer Design (ICCD)}, year={2015}, pages={311-318} }