Effective floating-point calculation engines intended for the FPGA-based HIL simulation

@article{Bachir2012EffectiveFC,
  title={Effective floating-point calculation engines intended for the FPGA-based HIL simulation},
  author={T. O. Bachir and C. Dufour and J. B{\'e}langer and J. Mahseredjian and J. David},
  journal={2012 IEEE International Symposium on Industrial Electronics},
  year={2012},
  pages={1363-1368}
}
  • T. O. Bachir, C. Dufour, +2 authors J. David
  • Published 2012
  • Computer Science, Engineering
  • 2012 IEEE International Symposium on Industrial Electronics
Hardware-in-the-loop (HIL) simulation is an industrial practice that consists in testing a physical electronic control unit (ECU) against a real-time simulated model of a plant. Typical PWM applications run in the kHz range and can hardly be simulated using standard methods with the typical CPU time-steps that are at best in the 5-10 microseconds range. Migrating the computational load from a CPU to a Field Programmable Gate Array (FPGA) allows overcoming the limitation and achieving time-steps… Expand
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