Effective and Efficient Approach for Power Reduction by Using Multi-Bit Flip-Flops

@article{Shyu2013EffectiveAE,
  title={Effective and Efficient Approach for Power Reduction by Using Multi-Bit Flip-Flops},
  author={Y. Shyu and Jai-Ming Lin and Chun-Po Huang and Cheng-Wu Lin and Ying-Zu Lin and S. Chang},
  journal={IEEE Transactions on Very Large Scale Integration (VLSI) Systems},
  year={2013},
  volume={21},
  pages={624-635}
}
  • Y. Shyu, Jai-Ming Lin, +3 authors S. Chang
  • Published 2013
  • Computer Science
  • IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Power has become a burning issue in modern VLSI design. In modern integrated circuits, the power consumed by clocking gradually takes a dominant part. Given a design, we can reduce its power consumption by replacing some flip-flops with fewer multi-bit flip-flops. However, this procedure may affect the performance of the original circuit. Hence, the flip-flop replacement without timing and placement capacity constraints violation becomes a quite complex problem. To deal with the difficulty… Expand
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where he is currently pursuing the Ph.D. degree in electronic engineering. His current research interests include integrated circuit design, design automation for analog, and mixed-signal circuits
  • degree in electrical engineering from National Cheng Kung University (NCKU)
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Available: http://cad_contest.cs. nctu.edu.tw/cad11 Ya-Ting Shyu received the M.S. degree in electrical engineering from
  • 2008, where she is pursuing the Ph.D. degree in electronic engineering. Her current research interests include integrated circuit design, design automation for analog, and mixed-signal circuits
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