Effective Hardware-Based Two-Way Loop Cache for High Performance Low Power Processors

@inproceedings{Anderson2000EffectiveHT,
  title={Effective Hardware-Based Two-Way Loop Cache for High Performance Low Power Processors},
  author={Tim Anderson and Sanjive Agarwala},
  booktitle={ICCD},
  year={2000}
}
The increasing level of system-level integration coupled with the higher clock frequency of today’s processors is increasing the power consumption of VLSI integrated circuits more rapidly than improvements in IC manufacturing can reduce power consumption. This paper presents a method for reducing the power consumption of DSP processors through the introduction of a two-way decoded loop-cache. By retaining decoded instruction information from two loops, the method has been shown to eliminate an… CONTINUE READING
Highly Cited
This paper has 32 citations. REVIEW CITATIONS

From This Paper

Figures, tables, results, connections, and topics extracted from this paper.
21 Extracted Citations
3 Extracted References
Similar Papers

Citing Papers

Publications influenced by this paper.
Showing 1-10 of 21 extracted citations

Referenced Papers

Publications referenced by this paper.
Showing 1-3 of 3 references

Magione-Smith, “The Filter Cache: An energy efficient memory structure,

  • J. Kin, W. M. Gupta
  • Proceedings of the International Symposium on…
  • 1997

Similar Papers

Loading similar papers…