Early formal verification of conditional coverage points to identify intrinsically hard-to-verify logic

@article{Ho2008EarlyFV,
  title={Early formal verification of conditional coverage points to identify intrinsically hard-to-verify logic},
  author={Richard C. Ho and Michael Theobald and Martin M. Deneroff and Ron O. Dror and Joseph Gagliardo and David E. Shaw},
  journal={2008 45th ACM/IEEE Design Automation Conference},
  year={2008},
  pages={268-271}
}
Design verification of complex digital circuits typically starts only after the register-transfer level (RTL) description is complete. This frequently makes verification more difficult than necessary because logic that is intrinsically hard to verify, such as memories, counters and deep first-in, first-out (FIFO) structures, becomes immutable in the design… CONTINUE READING