EURETILE 2010-2012 summary: first three years of activity of the European Reference Tiled Experiment

  title={EURETILE 2010-2012 summary: first three years of activity of the European Reference Tiled Experiment},
  author={Pier Stanislao Paolucci and Iuliana Bacivarov and Gert Goossens and Rainer Leupers and Fr{\'e}d{\'e}ric Rousseau and Christoph Schumacher and Lothar Thiele and Piero Vicini},
Abstract This is the summary of first three years of activity of the EURETILE FP7 project 247846. EURETILE investigates and implements brain-inspired and fault-tolerant foundational innovations to the system architecture of massively parallel tiled computer architectures and the corresponding programming paradigm. The execution targets are a many-tile HW platform, and a many-tile simulator. A set of SW process - HW tile mapping candidates is generated by the holistic SW tool-chain using a… 

EURETILE Design Flow: Dynamic and Fault Tolerant Mapping of Multiple Applications Onto Many-Tile Systems

The capability of the design flow to exploit the parallelism of many-tile architectures with various embedded and high performance computing benchmarks targeting the virtual EURETILE platform with up to 192 tiles is demonstrated.

Programming Framework for Reliable and Efficient Embedded Many-Core Systems

It is shown that the properties of the proposed programming model can be leveraged to develop a design, optimization, and synthesis process for embedded many-core SoCs that enables the system to utilize its computing power efficiently.

legaSCi: Legacy SystemC Model Integration into Parallel Simulators

A methodology to support simulation creators to face the challenge of integrating legacy models into parallel SystemC environments is proposed and a speedup of 2.13× is demonstrated, without having to change the individual models of the simulator.

Towards Exploiting Intra-Application Dynamism using an H . 264 Codec

This work argues that run-time dynamism can be achieved by balancing the tradeo between execution time and compression rate, and proposes a frame pipelining scheme as a means of increasing the encoder's performance, and calculates the maximum theoretical speedup that it can achieve.

A heterogeneous many-core platform for experiments on scalable custom interconnects and management of fault and critical events, applied to many-process applications: Vol. II, 2012 technical report

This volume covers several topics, among which: a system for awareness of faults and critical events on experimental heterogeneous many-core hardware platforms, and the initial stages of design of a new DNP generation onto a 28nm FPGA.

Power, Energy and Speed of Embedded and Server Multi-Cores applied to Distributed Simulation of Spiking Neural Networks: ARM in NVIDIA Tegra vs Intel Xeon quad-cores

This short note regards a comparison of instantaneous power, total energy consumption, execution time and energetic cost per synaptic event of a spiking neural network simulator (DPSNN-STDP)

Design of multicore HEVC decoders using actor-based dataflow models and OpenMP

A new back-end for the Open Reconfigurable Video Coding CAL Actor Language compiler framework (Orcc) is explained, which uses the OpenMP API instead of the pthreads library to automatically generate C code for any multicore architecture with OpenMP support.

APEnet+ 34 Gbps data transmission system and custom transmission logic

PAPEnet+ is a point-to-point, low-latency, 3D-torus network controller integrated in a PCIe Gen2 board based on the Altera Stratix IV FPGA providing deadlock-free routing and systemic awareness of faults.



Semi-automation of Configuration Files Generation for Heterogeneous Multi-tile Systems

The need to automate the whole configuration process of binary generation flows through the study of two important configuration aspects: the memory mapping and communication configurations is addressed.

Embedding formal performance analysis into the design cycle of MPSoCs for real-time streaming applications

An MPSoC software design flow that allows for automatically generating the system implementation, together with an analysis model for system verification, is presented and modular performance analysis (MPA) is integrated into the distributed operation layer (DOL) MP soC programming environment.

Dynamic Power-Aware Mapping of Applications onto Heterogeneous MPSoC Platforms

This study shows that deriving approximative solutions with a constant worst-case approximation factor in polynomial time is not achievable unless P = NP, even if a feasible task mapping is provided as an input.

SHAPES:: a tiled scalable software hardware architecture platform for embedded systems

The SHAPES routing fabric connects on-chip and off-chip tiles, weaving a distributed packet switching network, and the SW challenge is to provide a simple and efficient programming environment for tiled architectures.

Scenario-based design flow for mapping streaming applications onto on-chip many-core systems

The distributed application layer is presented, a scenario-based design flow for mapping a set of applications onto heterogeneous on-chip many-core systems and the proposed design flow is applied to design and optimize a picture-in-picture software.

Parallelizing SystemC Kernel for Fast Hardware Simulation on SMP Machines

A parallel SystemC simulation kernel is presented, which is implemented using parallel programming techniques and leverages the parallel execution capabilities of multi-core machines to speed up hardware simulation.

A System Framework for the Design of Embedded Software Targeting Heterogeneous Multi-core SoCs

  • X. GuerinF. Pétrot
  • Computer Science
    2009 20th IEEE International Conference on Application-specific Systems, Architectures and Processors
  • 2009
This work’s contribution is a component-based system framework that provides high-level system services for embedded software applications with few impacts on the memory usage and performances, thanks to strong interfaces that enable the reuse of existing software elements and facilitate the support of multiple hardware platforms.

Platform-based software design flow for heterogeneous MPSoC

A platform-based software design flow able to efficiently use the resources of the architecture and allowing easy experimentation of several mappings of the application onto the platform resources is proposed, which increases productivity and preserves design quality.

Virtual Manycore platforms: Moving towards 100+ processor cores

This special session deals with Manycore virtual platforms from several different perspectives, highlighting new research approaches for high speed simulation, tool and IP marketing opportunities, as well as real life virtual platform needs of industrial end users.

Backend for virtual platforms with hardware scheduler in the MAPS framework

This paper analyzes MAPS retargetability by adding a new backend for a heterogeneous MPSoC with the OSIP hardware scheduler and exports high level debugging information that is included in an environment for application debugging based on virtual platforms.