EURETILE 2010-2012 summary: first three years of activity of the European Reference Tiled Experiment

@article{Paolucci2013EURETILE2S,
  title={EURETILE 2010-2012 summary: first three years of activity of the European Reference Tiled Experiment},
  author={Pier Stanislao Paolucci and Iuliana Bacivarov and Gert Goossens and Rainer Leupers and Fr{\'e}d{\'e}ric Rousseau and Christoph Schumacher and Lothar Thiele and Piero Vicini},
  journal={ArXiv},
  year={2013},
  volume={abs/1305.1459}
}
Abstract This is the summary of first three years of activity of the EURETILE FP7 project 247846. EURETILE investigates and implements brain-inspired and fault-tolerant foundational innovations to the system architecture of massively parallel tiled computer architectures and the corresponding programming paradigm. The execution targets are a many-tile HW platform, and a many-tile simulator. A set of SW process - HW tile mapping candidates is generated by the holistic SW tool-chain using a… 

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References

SHOWING 1-10 OF 135 REFERENCES

Semi-automation of Configuration Files Generation for Heterogeneous Multi-tile Systems

The need to automate the whole configuration process of binary generation flows through the study of two important configuration aspects: the memory mapping and communication configurations is addressed.

Embedding formal performance analysis into the design cycle of MPSoCs for real-time streaming applications

An MPSoC software design flow that allows for automatically generating the system implementation, together with an analysis model for system verification, is presented and modular performance analysis (MPA) is integrated into the distributed operation layer (DOL) MP soC programming environment.

Dynamic Power-Aware Mapping of Applications onto Heterogeneous MPSoC Platforms

This study shows that deriving approximative solutions with a constant worst-case approximation factor in polynomial time is not achievable unless P = NP, even if a feasible task mapping is provided as an input.

SHAPES:: a tiled scalable software hardware architecture platform for embedded systems

The SHAPES routing fabric connects on-chip and off-chip tiles, weaving a distributed packet switching network, and the SW challenge is to provide a simple and efficient programming environment for tiled architectures.

Scenario-based design flow for mapping streaming applications onto on-chip many-core systems

The distributed application layer is presented, a scenario-based design flow for mapping a set of applications onto heterogeneous on-chip many-core systems and the proposed design flow is applied to design and optimize a picture-in-picture software.

Parallelizing SystemC Kernel for Fast Hardware Simulation on SMP Machines

A parallel SystemC simulation kernel is presented, which is implemented using parallel programming techniques and leverages the parallel execution capabilities of multi-core machines to speed up hardware simulation.

A System Framework for the Design of Embedded Software Targeting Heterogeneous Multi-core SoCs

  • X. GuerinF. Pétrot
  • Computer Science
    2009 20th IEEE International Conference on Application-specific Systems, Architectures and Processors
  • 2009
This work’s contribution is a component-based system framework that provides high-level system services for embedded software applications with few impacts on the memory usage and performances, thanks to strong interfaces that enable the reuse of existing software elements and facilitate the support of multiple hardware platforms.

Platform-based software design flow for heterogeneous MPSoC

A platform-based software design flow able to efficiently use the resources of the architecture and allowing easy experimentation of several mappings of the application onto the platform resources is proposed, which increases productivity and preserves design quality.

Virtual Manycore platforms: Moving towards 100+ processor cores

This special session deals with Manycore virtual platforms from several different perspectives, highlighting new research approaches for high speed simulation, tool and IP marketing opportunities, as well as real life virtual platform needs of industrial end users.

Backend for virtual platforms with hardware scheduler in the MAPS framework

This paper analyzes MAPS retargetability by adding a new backend for a heterogeneous MPSoC with the OSIP hardware scheduler and exports high level debugging information that is included in an environment for application debugging based on virtual platforms.
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