ETSOI CMOS for system-on-chip applications featuring 22nm gate length, sub-100nm gate pitch, and 0.08µm2 SRAM cell

@article{Cheng2011ETSOICF,
  title={ETSOI CMOS for system-on-chip applications featuring 22nm gate length, sub-100nm gate pitch, and 0.08µm2 SRAM cell},
  author={Kangguo Cheng and Ali Khakifirooz and Pranita Kulkarni and Shom Ponoth and B. S. Haran and Akhilesh Kumar and Thomas N. Adam and Alexander Reznicek and Nicolas Loubet and Hong He and James Kuss and M. Wang and T. M. Levin and Frederic Monsieur and Qing Gary Liu and Ramaswamy Sreenivasan and Jin Cai and Anne Kimball and Sunkist Mehta and Scott Luning and Yada Zhu and Zhengmao Zhu and T. Yamamoto and Andres Bryant and C. -H. Lin and S. Naczas and Hemanth Jagannathan and L. F. Edge and S. Allegret-Maret and Amol Dube and Sivananda Kanakasabapathy and Stefan Schmitz and Atsushi Inada and S. Seo and Mark V. Raymond and Zeyulin Zhang and Atsushi Yagishita and James J. Demarest and J. Li and M. Hopstaken and Nathaniel Berliner and Alicia Upham and Ryan C Johnson and Steven J. Holmes and Theodorus E. Standaert and Maria Brak. Smalley and Noah Zamdmer and Zhibin Ren and T. Wu and Huiming Bu and Vamsi K. Paruchuri and D. K. Sadana and V. Narayanan and Wilfried E. Haensch and June O'Neill and Terence B. Hook and Mukesh Khare and Bruce B. Doris},
  journal={2011 Symposium on VLSI Circuits - Digest of Technical Papers},
  year={2011},
  pages={128-129}
}
For the first time we report extremely thin SOI (ETSOI) CMOS with 22 nm gate length (L<inf>G</inf>) and sub-100 nm contacted gate pitch for system-on-chip (SoC) applications. Multi-V<inf>t</inf> transistors are demonstrated with competitive drive currents (NFET/PFET) of 1150/1050 µA/µm at I<inf>off</inf> = 100 nA/µm for high performance (HP) and 920/880 µA/µm at I<inf>off</inf> = 1 nA/µm for low power (LP), respectively, at V<inf>DD</inf> = 1 V. High density 6-T SRAM cells down to 0.08 µm<sup>2… CONTINUE READING
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