ESD protection for advanced CMOS SOI technologies

Abstract

In this paper we describe a 90 nm SOI ESD protection network and design methodology including both device and circuit level characterization data. We compare TLP results of SOI MOSFETs and diodes to bulk devices. We present a new response surface method to optimize device sizes in the ESD networks and show circuit level data comparing TLP test results and… (More)

13 Figures and Tables

Topics

  • Presentations referencing similar topics