ESD protection design on analog pin with very low input capacitance for high-frequency or current-mode applications

@article{Ker2000ESDPD,
  title={ESD protection design on analog pin with very low input capacitance for high-frequency or current-mode applications},
  author={Ming-Dou Ker and Tung-Yang Chen and Chung-Yu Wu and Hun Hsien Chang},
  journal={IEEE Journal of Solid-State Circuits},
  year={2000},
  volume={35},
  pages={1194-1199}
}
An electrostatic discharge (ESD) protection design is proposed to solve the ESD protection challenge to the analog pins: for high-frequency or current-mode applications, By including an efficient power-rails clamp circuit in the analog input/output (I/O) pin, the device dimension (W/L) of an ESD clamp device connected to the I/O pad in the analog ESD protection circuit can be reduced to only 50/0.5 (/spl mu/m//spl mu/m) in a 0.35-/spl mu/m silicided CMOS process, but it can sustain the human… CONTINUE READING
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