ESD protection design of low-voltage-triggered p-n-p devices and their failure modes in mixed-voltage I/O interfaces with signal levels higher than VDD and lower than VSS

@article{Ker2005ESDPD,
  title={ESD protection design of low-voltage-triggered p-n-p devices and their failure modes in mixed-voltage I/O interfaces with signal levels higher than VDD and lower than VSS},
  author={Ming-Dou Ker and Wei-Jen Chang},
  journal={IEEE Transactions on Device and Materials Reliability},
  year={2005},
  volume={5},
  pages={602-612}
}
Electrostatic discharge (ESD) protection design for mixed-voltage I/O interfaces with the low-voltage-triggered p-n-p (LVTp-n-p) device in CMOS technology is proposed. The LVTp-n-p, by inserting N+ or P+ diffusion across the junction between N-well and P-substrate of the p-n-p device, is designed to protect the mixed-voltage I/O interfaces for signals with… CONTINUE READING