ESD-immunity evaluations of a 40 V nLDMOS with embedded SCRs in the drain side


The impacts of current-path variation on the ESD robustness of nLDMOS devices as the drain-side modulation by a 0.18 μm/40 V process are evaluated in this paper. From the transmission-line-pulsing (TLP) measurement, the secondary breakdown current (It2) of an nLDMOS with the drain-side embedded SCR structure & "pnp" arrangement (DUT-2) increased from 2.498… (More)

3 Figures and Tables


  • Presentations referencing similar topics