ESD design challenges and strategies in deeply-scaled integrated circuits

@article{Cao2009ESDDC,
  title={ESD design challenges and strategies in deeply-scaled integrated circuits},
  author={Shuqing Cao and Tze Wee Chen and Stephen G. Beebe and Robert W. Dutton},
  journal={2009 IEEE Custom Integrated Circuits Conference},
  year={2009},
  pages={681-688}
}
Challenges of design window shrinkage in deeply scaled silicon technologies are addressed by improving design, characterization, and modeling of I/O and ESD devices, and by developing ESD robustness and circuit performance co-design methodologies. Advanced ESD metrology methods are reviewed and their applications in providing key information for reliability modeling are investigated. Package and wafer level CDM correlation issues are examined. 

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