EIE: Efficient Inference Engine on Compressed Deep Neural Network

@article{Han2016EIEEI,
  title={EIE: Efficient Inference Engine on Compressed Deep Neural Network},
  author={Song Han and Xingyu Liu and Huizi Mao and Jing Pu and A. Pedram and M. Horowitz and W. Dally},
  journal={2016 ACM/IEEE 43rd Annual International Symposium on Computer Architecture (ISCA)},
  year={2016},
  pages={243-254}
}
  • Song Han, Xingyu Liu, +4 authors W. Dally
  • Published 2016
  • Computer Science
  • 2016 ACM/IEEE 43rd Annual International Symposium on Computer Architecture (ISCA)
State-of-the-art deep neural networks (DNNs) have hundreds of millions of connections and are both computationally and memory intensive, making them difficult to deploy on embedded systems with limited hardware resources and power budgets. While custom hardware helps the computation, fetching weights from DRAM is two orders of magnitude more expensive than ALU operations, and dominates the required power. Previously proposed 'Deep Compression' makes it possible to fit large DNNs (AlexNet and… Expand
SparCE: Sparsity Aware General-Purpose Core Extensions to Accelerate Deep Neural Networks
High-Efficiency Convolutional Ternary Neural Networks with Custom Adder Trees and Weight Compression
Throughput Optimizations for FPGA-based Deep Neural Network Inference
Compressing DMA Engine: Leveraging Activation Sparsity for Training Deep Neural Networks
DUET: Boosting Deep Neural Network Efficiency on Dual-Module Architecture
  • Liu Liu, Zheng Qu, +6 authors Yuan Xie
  • Computer Science
  • 2020 53rd Annual IEEE/ACM International Symposium on Microarchitecture (MICRO)
  • 2020
Data-Driven Neuromorphic DRAM-based CNN and RNN Accelerators
BINARY DEEP NEURAL NETWORKS
EDEN: Enabling Energy-Efficient, High-Performance Deep Neural Network Inference Using Approximate DRAM
...
1
2
3
4
5
...

References

Going Deeper with Embedded FPGA Platform for Convolutional Neural Network