EGRA: A Coarse Grained Reconfigurable Architectural Template

  title={EGRA: A Coarse Grained Reconfigurable Architectural Template},
  author={Giovanni Ansaloni and Paolo Bonzini and Laura Pozzi},
  journal={IEEE Transactions on Very Large Scale Integration (VLSI) Systems},
  • Giovanni Ansaloni, Paolo Bonzini, Laura Pozzi
  • Published 2011
  • Computer Science
  • IEEE Transactions on Very Large Scale Integration (VLSI) Systems
  • Reconfigurable arrays combine the benefit of spatial execution, typical of hardware solutions, with that of programmability, present in microprocessors. When mapping software applications (or parts of them) onto hardware, however, fine-grain arrays, such as field-programmable gate arrays (FPGAs), often provide more flexibility than is needed, and do not implement coarser-level operations efficiently. Therefore, coarse grained reconfigurable arrays (CGRAs) have been proposed to this aim. Most… CONTINUE READING
    91 Citations
    Coarse-Grained Reconfigurable Array Architectures
    • 60
    • PDF
    Application-specific coarse-grained reconfigurable array: architecture and design methodology
    • 4
    • Highly Influenced
    Integrated Kernel Partitioning and Scheduling for Coarse-Grained Reconfigurable Arrays
    • 20
    • PDF
    Flexible reconfigurable architecture for DSP applications
    • 6
    Design and synthesis of reconfigurable control-flow structures for CGRA
    • 2
    Coarse-Grained Reconfigurable Array Architectures
    • 18
    • PDF
    Memory-Aware Loop Mapping on Coarse-Grained Reconfigurable Architectures
    • 19
    • PDF


    Design and Architectural Exploration of Expression-Grained Reconfigurable Arrays
    • 25
    • PDF
    Heterogeneous coarse-grained processing elements: A template architecture for embedded processing acceleration
    • 9
    • PDF
    Architecture exploration for a reconfigurable architecture template
    • 180
    Design and Implementation of the MorphoSys Reconfigurable Computing Processor
    • 139
    • PDF
    A dynamically adaptive DSP for heterogeneous reconfigurable platforms
    • 54
    • PDF
    Design methodology for a tightly coupled VLIW/reconfigurable matrix architecture: a case study
    • 156