EFFECTS OF NoC ARCHITECTURAL PARAMETERS IN MPSoC PERFORMANCE

Abstract

The goal of this end of term work is to evaluate the impact of the Network-on-Chip (NoC) parameters over the performance of applications on Multiprocessors Systems-on-Chip (MPSoCs). Nowadays, MPSoCs have so many constraints of performance that bus-based communications are not able to achieve the full potential of MPSoCs. Therefore, the adoption of networks-on-chip (NoCs) is a trend for the communication infrastructure in MPSoCs due to their performance compared to bus-based architectures and scalability compared to crossbar-based architectures. However, we were not able to find any reference in the state-of-the-art evaluating the impact of NoC parameters in the performance of applications running in MPSoCs. This work proposes a simulation-based monitoring method to evaluate network performance. Such monitoring collects performance results for different MPSoC applications scenarios, and for each scenario network parameters such as buffer size, routing algorithm and topology vary. The goal is to correlate NoC parameters with the MPSoC performance. This work adopts the HERMES NoC and the HeMPS MPSoC and tries to answer the following question: “ how does a given NoC parameter affect the performance of the MPSoC?”

31 Figures and Tables

Cite this paper

@inproceedings{Silva2013EFFECTSON, title={EFFECTS OF NoC ARCHITECTURAL PARAMETERS IN MPSoC PERFORMANCE}, author={Douglas R. G. Silva and Bruno S. Oliveira and Fernando Gehm Moraes}, year={2013} }