EECache: A Comprehensive Study on the Architectural Design for Energy-Efficient Last-Level Caches in Chip Multiprocessors

@article{Cheng2015EECacheAC,
  title={EECache: A Comprehensive Study on the Architectural Design for Energy-Efficient Last-Level Caches in Chip Multiprocessors},
  author={Hsiang-Yun Cheng and Matthew Poremba and Narges Shahidi and Ivan Stalev and Mary Jane Irwin and Mahmut T. Kandemir and Jack Sampson and Yuan Xie},
  journal={TACO},
  year={2015},
  volume={12},
  pages={17:1-17:22}
}
Power management for large last-level caches (LLCs) is important in chip multiprocessors (CMPs), as the leakage power of LLCs accounts for a significant fraction of the limited on-chip power budget. Since not all workloads running on CMPs need the entire cache, portions of a large, shared LLC can be disabled to save energy. In this article, we explore different design choices, from circuit-level cache organization to microarchitectural management policies, to propose a low-overhead runtime… CONTINUE READING
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