ECI: a Customizable Cache Coherency Stack for Hybrid FPGA-CPU Architectures

@article{Ramdas2022ECIAC,
  title={ECI: a Customizable Cache Coherency Stack for Hybrid FPGA-CPU Architectures},
  author={Abishek Ramdas and Michael J. Giardino and Runbin Shi and Adam Turowski and David A. Cock and Gustavo Alonso and Timothy Roscoe},
  journal={ArXiv},
  year={2022},
  volume={abs/2208.07124}
}
Unlike other accelerators, FPGAs are capable of supporting cache coherency, thereby turning them into a more powerful architectural option than just a peripheral accelerator. However, most existing deployments of FPGAs are either non-cache coherent or support only an asymmetric design where cache coherency is controlled from the CPU. Taking advantage of a recently released two socket CPU-FPGA architecture, in this paper we describe A Customizable Caching Interface (ACCI), a flexible… 
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