Dynamically Trading Frequency for Complexity in a GALS Microprocessor

@article{Dropsho2004DynamicallyTF,
  title={Dynamically Trading Frequency for Complexity in a GALS Microprocessor},
  author={Steven G. Dropsho and Greg Semeraro and David H. Albonesi and Grigorios Magklis and Michael L. Scott},
  journal={37th International Symposium on Microarchitecture (MICRO-37'04)},
  year={2004},
  pages={157-168}
}
Microprocessors are traditionally designed to provide "best overall" performance across a wide range of applications and operating environments. Several groups have proposed hardware techniques that save energy by "downsizing" hardware resources that are underutilized by the current application phase. Others have proposed a different energy-saving approach: dividing the processor into domains and dynamically changing the clock frequency and voltage within each domain during phases when the full… CONTINUE READING

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Key Quantitative Results

  • Measuring across a broad suite of application benchmarks, we find that configuring our adaptive GALS processor just once per application yields 17.6% better performance, on average, than that of the "best overall" fully synchronous design.
  • that con.guring our adaptive GALS pro­cessor just once per application yields 17.6% better per­formance, on average, than that of the best overall fully synchronous design.
  • Despite these handicaps, we demonstrate overall performance im­provements of 17.6% with respect to the best fully syn­chronous design using only whole-program adaptation of the instruction cache, branch predictor, integer issue queue, .oating-point issue queue, and data / L2 caches.

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